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Technical Paper

8Gbps CMOS Pin Electronics Hardware Macro with Simultaneous Bi-directional Capability

Author Technology Development Group 5th R&D Department FT Technology R&D Section Shoji Kojima and others
Summary In this paper, we present a small sized CMOS pin-electronics hardware macro applicable to 8Gbps real-time functional testing. The macro includes a driver, comparators, DACs, and control logic embedded within an area of size 2mm x 1.6mm. As the macro is implemented on a 65nm standard CMOS process, it can be implemented together with pattern generators and timing generators to realize a single chip pin electronics solution. Moreover, the macro is capable of simultaneous bi-directional (SBD) signaling, which greatly reduces test time. A simple and reliable method to evaluate SBD is also discussed. We have applied our macro to a test chip to prove that the macro is applicable to an 8Gbps test system.
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RNA: Advanced Phase Tracking Method for Digital Waveform Reconstruction

Author System Solution Group SoC System Engineering COE (Center Of Expertise) Hideo Okawara
Summary This paper describes how to measure an eye diagram by using ATE (Automated Test Equipment) digital channel and to do a correlation with an oscilloscope for over-Giga-bps class high speed digital interfaces. The novel method named RNA (Recovering aNAlysis) is a post processing method to perform "phase tracking" in the eye diagram measurement on an ATE which does not have a CDR (Clock Data Recovery) hardware integrated. The RNA is an enhancement of the method named DNA (Data aNAlysis) that constructs an eye diagram by coherent waveform reconstruction with utilizing an ATE digital channel. The DNA is an elegant method to reconstruct digital signal waveform and its eye diagram; however it is not immune to slow jitter or wander of signal. In recent high speed digital interfaces, jitter tolerance is very critical so that the DNA is insufficient for coping with test devices containing slow jitter. The RNA is an enhanced DNA by implementing software quasi-CDR described in this paper. It significantly expands the application coverage. The eye diagram processed by this method is improved and good for parametric measurement such as rise time/fall time tests. Especially, it allows to do an easy correlation to the eye measured by an oscilloscope. Therefore the transition from bench systems to ATE for production test becomes smooth and efficient.
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Development of high-power pulsed fiber lasers

Author Advantest Laboratories Ltd. Naoya Tsukahara and others
Summary The high power pulsed laser has an important role as a small, robust and maintenance-free light source to be built into medical diagnostics equipment such as photoacoustic imaging systems. In this research, we have successfully built a transportable realtime imaging prototype system for the first time, by developing a Q switch Yb (ytterbium) doped fiber laser to obtainpulse energy in the order of mJ/pulse, and moreover, are developing a wavelength conversion module to match the pulsed light with the light absorption wavelength of hemoglobin.
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The resonance adjustment methods for magnetically coupled resonance wireless power transfer

Author New Business Enabling Division WiPS Project Yuki Endo and others
Summary Wireless charging is a focus of recent discussions, particularly the magnetic resonant coupling method is expected as a capable mid-range wireless power transfer technology. However, the required tuning function of the resonance frequency for the resonator was challenging. In this paper, we describe an Advantest's unique technology that easily solves this issue, Automatic Tuning Assist Circuit (ATAC).
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Application

ECOTsTM the Evolutionary Factory Automation tool

Author Common Solution, System Solution Group Application & Tool Katsuya Takano and others
Summary We have developed ECOTsTM (Easy, Convenient Operation Tools), which provides easy and convenient tester operation as a standardized mass production tool in the semiconductor testing process. ECOTsTM is designed for efficient operation in the semiconductor testing process with high scalability by easy customization. In this paper, the ease of customization and benefit of deployment of ECOTsTM are discussed.
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High Efficiency Massive Parallel Test Capability of T2000 Integrated Massive Parallel test solution

Author SoC Test Business Group 2nd R&D Department PFA Section Koji Hara
Summary Recent analog devices, micro computers with built-in flash memory and smart card ICs, which have shown remarkable progress, are very cost sensitive devices with a strong emphasis on manufacturing cost. The requirements for reduction in testing cost is increasing for those devices from the market. We have now reduced 50% of the testing cost by the introduction of universal pin architecture and improvement in hardware.
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Other

Addressing the Challenges of 3D IC Package Handling for Automated Test

Author Director, Handling Systems, Advantest America, Inc. Zain Abadin
Summary

3D integrated circuit (IC) packages offer major improvements in silicon device performance such as higher density, lower cost, lower power consumption, and smaller form factor. However before 3D (and even 2.5D) IC packages can achieve high production volumes, the challenges of handling these packages for automated final test must be overcome. For example, the new packaging technology combines:

  • Heterogeneous stacked devices with high levels of power dissipation which creates the risk of overheating during testing,
  • Finer pin/pad pitches which create the potential for misalignment during insertion, and
  • Thinner dies which require application of lower controlled forces during handling.

Therefore, the next generation of automated test handlers needs to provide thermal control, vision alignment and soft touch handling technology to address these challenges and accelerate the migration of 3D stacked devices into full-scale production.
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