Probo No.42 Details
Technical Paper
30-Gb/s Optical and Electrical Test Solution for High-Volume Testing
| Author | Technology Development Group 5th R&D Department Daisuke Watanabe others |
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| Summary | To enable high-volume testing of LSIs with high-speed optical and electrical interfaces, we developed a proof-of-concept device of an optical LSI test system for use in mass-production testing. Key technologies include high-density and high-performance optical functional devices and a device interface enabling simultaneous connection of optical and electrical interfaces. Our proposed system, using PLZT thin-film modulators, supports multi-channel optical bit-error-rate (BER) testing of devices with signal rates up to 30 Gb/s with results that correlate reasonably well with those measured by conventional BER test system (BERTs). Moreover, our newly devel-oped opto-electronic hybrid interface socket enables high-volume testing with good insertion losses and repeatability. Additionally, our flexible system architec-ture can be used for testing at various laser wavelengths and with various parameters for optical LSIs in combi-nation with off-the-shelf instruments for meeting optical characterization requirements. |
| Key Words | Not Specified |
A New Method for Off-Chip or On-Die Timing Noise Measurement
| Author | Advantest Laboratories, Ltd. Takahiro Yamaguchi others |
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| Summary | This paper introduces a new Level-Crossing ADC (LCADC) architecture which employs the novel use of a clocked comparator. The proposed LCADC can measure a timing noise spectrum with wide dynamic range and wide frequency range. An extension of the underlying theory of the performance measurement of an LCADC is also included. |
| Key Words | Not Specified |
Time to Market Reduction from Pre-/Post-Silicon Verification to Production on ATE
| Author | SoC Test Business Group Business Development Department Atsuo Sawara |
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| Summary | Recently complexities of system-on chip (SoC) devices make their production tests more difficult and also design verification time is getting larger than before. Although technologies of design for test (DFT) are improving, it is quite difficult to say that failure analysis is also improving due to a restriction of DFT circuit implementations. We have developed a new solution against most of semiconductor companies have a concern of their engineering resources. In this paper, we introduce a new Post-Silicon Verification approach based on new pattern generator and EDA-Link technologies. |
| Key Words | Not Specified |
Technical Description
Why Next-Generation NAND Flash Requires a Dedicated Test Solution
| Author | Advantest America, Inc. Product Marketing Ken Hanh Lai |
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| Summary | NAND Flash has been evolving in the densities and the speed due to various technology innovations. On the other hand per-bit market price of NAND Flash has been dropping. The development of the product which improves test quality and throughput without raising the test cost is required to tester maker. In order to meet the requirement, tester maker needs to develop the dedicated tester which is specialized in NAND Flash test in functionality and performance. In this article, market trend and technology trend of NAND Flash are described first. Next to that, 10 items (features and performances) which are required for next generation NAND Flash testing are expounded. And regarding especially important 4 items, more details are described. |
| Key Words | Not Specified |