Probo No.47 Details
Technical Paper
Known-Good-Die Test Methods for Large, Thin, High-Power Digital Devices
| Author | Advantest, Inc. San Jose, CA, USA Dave Armstrong others |
|---|---|
| Summary | The testing of large high-power devices which are destined for 2.5D or 3D applications requires many new techniques and solutions. This paper discusses some of the tradeoffs we looked at when striving to achieve true Known-Good-Devices (KGD) of large thin high-power logic devices. It is expected that the approach explored with this effort will significantly improve the post-assembly 2.5D/3D yield by bringing forward various high and low temperature tests which previously have not been possible to do. This paper discusses the challenges with wafer probing of this class of devices, analyzes the value of doing pre-insertion and/or partial assembly testing of this type of device. Also discussed in this paper are the various steps used to confirm the appropriateness of a recently introduced probe solution, Advantest HA1000, for meeting the demanding needs of singulated die level testing. |
| Key Words | Not Specified |
Modeling of contact resistance at very small contact point
| Author | Advantest Laboratories Ltd. Takeshi Tanaka others |
|---|---|
| Summary | Recently, as IC chips have become more highly integrated, their pads have become more miniaturized, with narrower pitch, and increased in number. Thereby, low contact resistance by using nonsliding probes is required. Thus, by modeling phenomenon at contact point that the load was impressed vertically, contact resistance was calculated theoretically. In this study, we introduce results that were compared with the theoretical values and the measurement values. |
| Key Words | Not Specified |
Application
ADC Linearity Measurement by Using Servo Method on the EVA100
| Author | ASD Test & Measurement System Business Group ASD Measurement System R&D Department Application R&D Section Hiroaki Kato |
|---|---|
| Summary | Linearity of analog to digital converter (hereafter ADC) which is not able to compensate is an important indicator for ADC manufacturers. Though there are many methods to test linearity of ADCs, we focused on Servo method which is accurate but is required long time to conduct. We fabricated it by using the EVA100 with hardware loop of the system. Our measuring target bit number of ADC is up to 18-bit. Thanks to the hardware loop, we could measure it less than 14 hours. It is said that it requires a few days to measure linearity of 18-bit ADC under some conditions. We are going to describe Servo method, implementation of the method on the EVA100 and results of measurement of linearity of 18-bit ADC in this paper. |
| Key Words | ADC、Linearity、DNL、INL、Servo、EVA100 |
High Speed and high precision ADC tests using the High Frequency AWG/DGT module of the EVA100 test system
| Author | Technology Development Group 9th R&D Department Yasuhide Kuramochi other |
|---|---|
| Summary | The dissemination of smartphones and other mobile wireless devices, and the increasing transmission of large-volume data, have led to the frequent use of ADCs (Analog to Digital Converters) combining high-speed operation of a few tens of MSps (Mega Samples per second) with high precision of 14?16 bits as ADCs for wireless base stations. To conduct testing of these ADCs at low cost, the authors have developed High Frequency AWG/DGT (referred to below as HF AWG and HF DGT). This paper introduces ADC test techniques using the characteristics of this module. |
| Key Words | Not Specified |
High-Density LSI Failure Analysis Technology using an Ultra-High Resolution TDR System
| Author | Terahertz System Business Division System R&D Department System R&D Section Masaichi Hashimoto other |
|---|---|
| Summary | Failure Analysis for high-density LSIs having a fine-package structure requires a resolution of several tens of μm to identify the wiring fault location. However, the resolution of existing time domain reflectometry (TDR) systems has been limited to around several hundreds of μm due to probe signal rise time and jitter constraints. To overcome these restrictions, we have developed a TDR system (TS9000 TDR option) having an ultra-high resolution of less than 5μm by applying electro-optical sampling (EOS) technology, which is indispensable for analysis of cutting-edge packages. In this paper we report on the TDR system and examples of analysis. |
| Key Words | TDR, EOS, TS9000, ultra-high resolution, high-density LSI, failure analysis |