Probo No.51 Details Probo No.51 Details

Technical Paper

Drain-induced barrier lowering in normally-off AlGaN-GaN MOSFETs with singleor double-recess overlapped gate

Author	Advantest Laboratories Ltd. Taku Sato others
Summary	We investigated drain-induced barrier lowering (DIBL) in normally-off AlGaN-GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) with a single- or a double-recess overlapped gate structure, in comparison with a conventional recess gate structure. The recess overlapped gate structures can suppress DIBL, where the double-recess is more advantageous for the DIBL suppression.
Key Words	Not Specified

A Stressed Eye Testing Module for Production Test of 30-Gbps NRZ Signal Interfaces

Author	FT Technology R&D Section 2, 5th R&D Department, Technology Development, Business Promotion Group Kiyotaka Ichiyama others
Summary	In high-speed data transmissions with small-amplitude signals, since jitter and noise in the transmitted signal may cause bit errors at receiver side, stressed eye testing which tests receivers with a degraded signal becomes very important. This paper introduces a stressed eye testing module for 30-Gbps nonreturn to zero (NRZ) signals. It can inject random jitter (RJ), sinusoidal jitter (SJ) and sinusoidal interference (SI) into the input signal for a receiver under test. A calibration method of RJ, SJ and SI values for the specified stressed bathtub curve is also proposed. This module can provide existing automatic test equipment with the stressed eye testing functions which can be applied to production testing.
Key Words	Not Specified

Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system

Author	Memory SE1, Memory System Engineering, System Solution Division, Sales Group Ryo Tamura others
Summary	A novel memory test system is needed for future STT-MRAM mass production that supports error bit analysis and its mode categorization on STT-MRAM chip measurement, as STTMRAM cell's switching is a probabilistic phenomenon based on quantum mechanics. In order to meet this requirement, we successfully developed a novel current measurement module on gigabit class memory test system that can measure the time domain switching current of each bit with nanosecond and microampere resolution. Moreover, we demonstrated the world's first results that our developed memory test system detects all error bits in fabricated STT-MRAM chip and categorizes error bit mode according to the switching characteristics of each error bit. This novel memory test system with the function of accurate and high speed time domain current measurement on the same level as single bit measurement equipment is expected to accelerate R&D and mass production of STT-MRAM and other applications such as ReRAM and PCM.
Key Words	Not Specified

Application

New Thermal Technology for a New Burn-in Test System

Author	CHL Group, Mechanical Design Department, Mechanical Engineering Division, Production Group Tsuyoshi Yamashita
Summary	To cope with the increase in heat produced due to enhanced performance of devices in recent years, a new refrigerator and new temperature control method for burn-in test systems have been developed, enabling support for thermal loads about 3 times the previous level, and further improvement of control stability. This method also minimizes the control parameter adjustment by technicians needed with the previous method, and simultaneously achieves reduction of downtime, reduction of manufacturing / maintenance man-hours, reduction of adjustment manhours for responding to the setup environment or individual differences, and minimization of power consumption to help protect the environment.
Key Words	Not Specified

T2000 IPS + GPWGD: a Measurement Technique with Ultra-High Dynamic Range for Hi-Res Audio

Author	Solution Section 1, Solution Department, System Planning Division, T2000 Business Unit, ATE Business Group Takahiro Nakajima others
Summary	In this paper, we introduce a measurement technique with ultrahigh dynamic range to achieve industry-leading levels of analog performance, by adding high-precision analog circuits such as a band elimination filter (BEF) at the front-end of T2000 general purpose waveform generator digitizer module (GPWGD). Furthermore, we can achieve twice (16 multi-site tests) the number of multi-sites compared to conventional systems, by combining it with a T2000 Integrated Power Solution (IPS) system. This solution makes it possible to support everything from characterization to mass production for power management ICs (PMICs) that support Hi-Res Audio.
Key Words	Not Specified