Probo No.52 Details
Technical Paper
High-resolution Time-domain Reflectometry Analysis in Back-end-of-line (BEOL) by Recursive Circuit Modelling
| Author | Advantest (Singapore) Pte .Ltd. Marketing & New Product Department Yang Shang others |
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| Summary | In the prevailing era of Internet of Things (IoT), the conventional failure analysis methodologies are more and more challenged by increased I/O density and data through-put with complex chip structures, such as 3D IC and 2.5D packaging technologies. Recently, impulse-based time-domain reflectometry (TDR) has gradually become a popular method to quickly localize a failure point in 2.5D/3D package with high resolution. However, it is still a big challenge to apply such TDR analysis for defect characterization inside the die. In this work, a recursive modeling technique is proposed to enable the TDR analysis inside the die to the front-end-of-line (FEOL) interface. |
| Key Words | Not Specified |
Technical Description
Development of high-voltage, high-current floating module with a maximum of 320 V and 18 channels
| Author | Business Promotion Group Technology Development Division 8th R&D Department DC R&D Section 1 Shigeyuki Takeda others |
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| Summary | Due to increasing pin counts resulting from higher voltage and functionality of automotive devices in recent years, test systems need to have higher voltage and more channels in their output/measurement voltage range. Therefore, we have realized higher voltage by increasing in-channel withstand voltage, and the number of stacking connections using a floating structure. The number of channels has been increased by newly developing a compact channel power supply and a hybrid IC for the I/O switch part, and by saving space in the mounting area through reduction of in-channel analog circuit power supplies. |
| Key Words | Not Specified |
Application
Test cell solution for reducing thermal spikes in semiconductor device testing
| Author | Sales Group System Solution Division 2nd SoC System Engineering SoC SE3 Takatoshi Yoshino others |
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| Summary | In testing semiconductor device such as large-scale CPU/GPUs, power consumption increases during functional testing, and the inside of the device sometimes generates heat. It is necessary to accurately control this temperature rise and test correctly under the guaranteed device under test (DUT) operating conditions. This paper describes a new technique for analyzing transitions in the junction temperature of the DUT in synchronization with test items, by enhancing sharing and synchronization of information between systems in a device testing environment (test cell) in which the semiconductor test equipment (tester) and the device handling equipment (handler) are connected. This paper also presents a feed-forward temperature control technique using that data. This technique is capable of handling device testing in which the timing of thermal spike occurrence is not constant from the start of the test. The effectiveness of this technique with an actual GPU device is also described. |
| Key Words | Not Specified |
Verizon 5G: Test challenges for next generation of mmWave communications using V93000 WaveScale RF
| Author | Advantest America, Inc. Max Seminario others |
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| Summary | This paper will study the PHY layer for the Verizon 5G standard. We will also go into details of the test challenges on testing at the RF frequencies used in the Verizon 5G standard. The differences between the Verizon 5G and the 3GPP 5G standards are also discussed in detail, as well as the new demodulation and debugging solutions provided by the V93000 WaveScale RF to easily and quickly test these 5G types of devices for both the Verizon and the 3GPP standards. |
| Key Words | Not Specified |
Test Time Analysis & Optimization on SmarTest8
| Author | Advantest China Co., Ltd. ADVANTEST Business Development&Center of Expertise, Asia Zexin Yan others |
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| Summary | Authors analyzed test time on ATE platform V93000 with tools on SmarTest8 like ‘TP360’ and 'operating sequence view'. Based on results of analysis, general procedure to optimize throughput is described with 5 real cases about analyze and optimize program in this paper. |
| Key Words | Not Specified |