网页内容展示网页内容展示

Technical Paper

Cherenkov-type phase matched terahertz wave generation from LiNbO₃ waveguide using mode-locked fiber laser and optical amplifier

Author	Advantest Laboratories Co., Ltd.　Takanori Okada others
Summary	We demonstrate Cherenkov-type phase-matched terahertz wave generation using a LiNbO₃ waveguide that incorporates a halfconic silicon prism, which efficiently generates broadband terahertz waves in a frequency range up to 7 THz with a pulse duration of 146 fs. We use a newly developed environmentally stable passively mode-locked fiber laser and an optical amplifier as a pulse compressor to generate stable high-intensity ultra-short pulses. As a result, optical pulses with a 50-fs pulse duration, an average output power of 50 mW, and a repetition rate of 50 MHz can be successfully generated.
Key Words	LiNbO₃ waveguide, Cherenkov-type phase-matched, half-conic silicon lens, terahertz source, femtosecond lasers, mode-locked fiber laser, optical soliton, erbium doped fiber amplifier

Software Execution Time Reduced by New Tester-per-Site Architecture Using High-performance CPU

Author	TP R&D Section 2, 2nd R&D Department, Technology Development Division, Technology Development Group, ATE Business Group Tomonori Senbon others
Summary	The conventional memory test system uses a System On Module (SOM: a computer for embedded applications with its basic features such as the CPU, chip set and memory being mounted in a single module) as its tester processor and is mounted in a digital module. This can achieve high-speed data communication and reduce the installation area of the test system, as the module is connected directly to a wide-area interface of the CPU. As, however, this method limits the power consumption and size of the CPU used, there are issues such as having lower basic performance than a general-purpose computer and making it more difficult to allocate computer resources in a flexible manner. For that reason, this paper proposes a new Tester-per-Site architecture of the memory test system to solve such issues. For its tester processor, the new architecture uses a server designed for a data center that has enough CPU performance to achieve both many-core configuration and faster operating frequencies. Multiport TBUS IF Card has also been developed to enable a Tester Bus Interface (TBUS IF: interface used to connect the tester processor and modules) to control many digital modules to maximize the many-core superiority. This allows you to control digital modules individually by CPU core and reduce the time required to execute software by building a system that can improve the CPU performance and allocate computer resources in a flexible manner.
Key Words	Not Specified

Test cost reduction according to Adaptive Probe Cleaning

Author	GAIA Development Center, Service Design Department, FS Business Division, Field Service Business Group　Hajime Sugimura
Summary	The devices to be inspected by ATE are becoming more sophisticated every year. Inspection costs have also been rising accordingly. Various attempts have been made to address this issue. Mainly, the optimization of test time, number of simultaneous measurements, test methods, equipment and fixtures have been the focus of attention. We have paid attention to the cost reduction of probe cards, which has not received much attention in the past. We developed Adaptive Probe Cleaning (APC) using A.I. and succeeded in this reduction. This paper introduces the technology and effects of APC.
Key Words	prober, probe card, A.I., inspection cost, test cost, on-line cleaning, sort test, wafer test

Technical Description

16 Gbaud PAM3 V93000 BOST solution for GDDR7

Author	5th R&D Department, Technology Development Division, Technology Development Group, ATE Business Group　Daisuke Watanabe others
Summary	GDDR7 standardized as a next generation graphic DRAM adopts PAM3 signaling and additional some data bits to enhance its memory interface bandwidth. Memory device venders require a solution to test the PAM3 for their early R&D phase. We have developed a BOST solution with V93000 digital modules which is capable of 16 Gbaud high-speed of PAM3 testing. This paper introduces its design concept and some evaluation results.
Key Words	Not Specified

Application

Accelerate the Test Program Development and Contribute to the TAT Reduction using T2000 RDK

Author	SoC Section 2, T2000 SE Department, System Solution Division, Sales Group　Yasunori Yamaguchi
Summary	RDK (Rapid Development Kit) has been released to make T2000 test program development easier and reduce the TAT. This paper introduces the evaluation result of RDK from usability and performance point of view, by converting from existing T2000 test program (OTPL + test class) to RDK style program.
Key Words	Not Specified